Hotfix SPB 16.50.016, Hotfix SPB 16.50.017 (2012) | 1.1 GB

Updates for Cadence SPB/OrCAD 16.50.000 - 16.50.015.
System requirements:
Package installed Cadence SPB / OrCAD 16.50.000 - 16.50.015
Compatible with Win7: Yes
Language: English

To install the latest updates, no need to install everything, just download and install the latest. But in previous versions of SPB happened that after the update appear "fresh" glitches, then try to install the previous one.

Improvements in:
DATE: 03-02-2012 HOTFIX VERSION: 017

867,859 ALLEGRO_EDITOR SHAPE Overlapping static and dynamic shape are out of date but display status shapes reports up to date
940 856 PSPICE ENVIRONMENT Simsrvr crashes when opening "Edit simulation profile" window from Capture 2nd time
951,657 FSP DESIGN_SETTINGS Support for new CPLD with Qualcomm flow
961,998 FSP MODEL_EDITOR Support for VRP and VRN as Target Pin Property
962,132 FSP DE-HDL_SCHEMATIC Symbol viewed in FSP has a different Pin sequence than in DEHDL Schematics
962,380 FSP OTHER Differential pairs of group contiguous pin cannot be synthesized
963,662 FSP OTHER "FPGA Port" does not match with the "Specify Net name"
965,353 FSP OTHER "This feature is not available" while printing PDF from Schematic or Files View.
967,418 ALLEGRO_EDITOR INTERACTIV Component gets mirrored when placed after using Reject
968,403 ALLEGRO_EDITOR SHAPE shape void element command does not work correctly
975,184 PDN_ANALYSIS PCB_STATICIRDROP Fail to do static ID Drop Analysis
975 674 CAPTURE PART_EDITOR Crash on saving an edited part with a different name, copied from another library
976,704 CONCEPT_HDL INFRA xcon and def files are not updated correctly although do hier_write
978,649 CONCEPT_HDL OTHER DEHDL crashes with highlight while cross-probing.
978,722 ALLEGRO_EDITOR OTHER ENH: Drafting text value should be same as given
978,754 SIG_INTEGRITY SIMULATION OrCAD PCB SI is not using custom stimulus
978,772 CONCEPT_HDL COPY_PROJECT CopyProject is changing the library order in the cpm file when you rename the library name
979,075 CONCEPT_HDL INFRA e and folders are getting created at cpm level on concepthdl in spb165
979,451 SIP_RF FTB V-SiP Arch constraints not passing Front2Back for differential pair assignment
979,458 CONCEPT_HDL CORE Add port Genview Move pin on block - pin name disappears
980,204 ALLEGRO_EDITOR SKILL different output value before and after the execution of axlLayerCreateCrossSection skill function
980,211 ALLEGRO_EDITOR MANUFACT Empty Dimension Group Subclass on package symbol is corrupting the symbol when placed on board file.
980,532 PDN_ANALYSIS PCB_STATICIRDROP PDN: PDNSIM_32BIT fail if no return path exist.
980,584 ALLEGRO_EDITOR PADS_IN mbs2brd crashes when translating the Mentor design to Allegro.
980,721 SIP_LAYOUT WIREBOND import of wirebond xml file with malformation does not indicate any error in the file
980,904 SIP_LAYOUT WIREBOND Why is min and max wire length in status window showing the same value which is not taken from the constraint settings
980,933 PCB_LIBRARIAN IMPORT_OTHER License call failed for feature Capture version 16.500 and quantity of a
981,156 APD GRAPHICS The cline display remains while moving a finger.
981,309 ALLEGRO_EDITOR OTHER Change DFA code so a perfect square is an ambigious condition and uses the most conservative value
981,345 SIP_LAYOUT DEGASSING Degassing causing strange voids.
981,436 ALLEGRO_EDITOR OTHER Unable to add cross section chart after deleting the chart with the delete command
981,756 ALLEGRO_EDITOR OTHER Associative Dimensioning: Change Text changes the Unit instead of Value
982,272 ALLEGRO_EDITOR OTHER Line Fattening is in incorrect license tier area
983,231 ALLEGRO_EDITOR OTHER Change Text in dimension Environment, is not working as desired
983,736 CONCEPT_HDL CONSTRAINT_MGR Voltage Sync property is being removed from CMGR during Back annotation due to PXL annotate net enabled
983,848 SIG_INTEGRITY OTHER Model names with a comma are not corrected
984,120 ALLEGRO_EDITOR MANUFACT Test prep crash Allego when using RMD on Existing Via column header
984,283 ALLEGRO_EDITOR SHAPE Allegro crashes when selecting a shape
DATE: 02-17-2012 HOTFIX VERSION: 016


840,105 PCB_LIBRARIAN USABILITY PTF subtype is getting changed when Save As option is used in PDV
873 075 PSPICE PROBE Decibel of FFT results are incorrect.
938 744 ADW COMPONENT_BROWSE Need ability to customize shopping cart columns to include any Part property
943 003 SCM REPORTS The dsreportgen command fails with network located project
961,530 ALLEGRO_EDITOR INTERACTIV The problem of Display measure command
962,157 CONCEPT_HDL CORE Where is the setting for enabling the Enable PSpice Simulator menu?
962,206 CONSTRAINT_MGR CONCEPT_HDL Import physical not passing all constraints from the board to frontend
968 205 PSPICE DEHDL_NETLISTER Change SPLIT_INST property to PSICE_SPLIT_INST for Quad Switch type of design.
968,509 PCB_LIBRARIAN METADATA Incorrect pinlist.txt was generated if DIFF_PAIR_PINS_POS / NEG was set.
969 450 LAYOUT TRANSLATORS OrCAD Layout to Allegro Translator crashes
969,997 CONSTRAINT_MGR CONCEPT_HDL ERROR (SPCOPK-1053): Cannot find a ppt part that matches the instance pro ~
971,193 CONSTRAINT_MGR UI_FORMS Copy and pasting a formula causes the application to crash on windows.
971,601 CONSTRAINT_MGR CONCEPT_HDL ERROR (SPCOPK-1053) and WARNING (SPCODD-66) because of directory structure
973,398 CONCEPT_HDL OTHER It should be not packaged with error while working the packaging process if the design has a ERROR
973 859 PSPICE ENCRYPTION Pspice crashes with encrypted model
973,938 PCB_LIBRARIAN VERIFICATION pc.db is missing
974,540 CONCEPT_HDL CORE Graphics updates are real slow
974 791 F2B DESIGNVARI Variants are not back-annotating to schematic and turning to?
974,818 ALLEGRO_EDITOR NC Backdrilling produces 0 plunges yet no errors reported.
974,945 ALLEGRO_EDITOR SKILL Why is axlPolyOperation is giving different result and not working
974,946 MODEL_INTEGRIT TRANSLATION ibis2signoise returns the error - Delay measurement fixture must contain V for ECL technology
975,396 CONCEPT_HDL CONSTRAINT_MGR Constraints are dropped after migrating from 16.3 to 16.5
975,633 ALLEGRO_EDITOR GRAPHICS 'dynamic_layer_visibility' option in 3D Viewer when checked or unchecked should not change (until next change)
975,720 ALLEGRO_EDITOR DRAFTING Datum dimension lines not adjusting to text move
975,745 ALLEGRO_EDITOR SKILL cdsServIpc different 16.2 vs 16.5 when Allegro exits
976,013 CONCEPT_HDL INFRA Power pin connection of FPGA symbol is missing in netlist.
976,058 CONCEPT_HDL COPY_PROJECT SCM Copy project does not create the con and dcf files in tbl_1 views
976,073 CONCEPT_HDL COPY_PROJECT All the constraint data is lost in the SCM copied design
976,160 CONCEPT_HDL CREFER Cref fails due to some Caeviews error in the design
976,204 ALLEGRO_EDITOR DRC_CONSTR Application falsely reporting Mechanical Pin Antipad to Shape Spacing DRC
976 448 F2B PACKAGERXL ERROR (SPCOPK-1069): Invalid POWER_GROUP property value
976,521 ALLEGRO_EDITOR DRC_CONSTR multi-thread update DRC causes the application to crash
976,838 SIG_INTEGRITY OTHER Unable to create XNET for highlighted nets on attached database even after assigning proper Signal Models.
977 517 F2B PACKAGERXL Export physical fails after update to 16.5 from 16.3
977,902 ALLEGRO_EDITOR DATABASE generate module is crashing allegro
978,652 ALLEGRO_EDITOR PADS_IN PADS_IN fails with ERROR: Finished with errors.
978,744 APD DEGASSING Some shapes will not DeGas on this design
979,940 SIP_LAYOUT OTHER SiP Layout Leadframe autobonding with profile selection
981 699 CAPTURE HELP Start Page still shows Hotfix 14 after installing Hotfix 15

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