Quartus II 11.1 SP1 Build 216 Altera Complete Design Suite Devices (ISO) | 4.52 GB

Enhancedsupport for Stratix V FPGA, namely: Supports GigE and SDI embeddedtransceivers; now support setting additional transceivers. parameters(receiver offset calibration, linear equalizer, and dynamicreconfiguration of PMA analog settings). Added debugging interface toexternal memory chips (Memory Interface Toolkit). The new facilityallegedly allows realtime track the performance of the memory subsystem.

Youcan choose the most efficient mode of operation of the memorycontroller, changing its settings. Added a debugging tool for thetransceiver (Transceiver Toolkit). Improved user interface managerchannels enables realtime monitor link status of receivers andtransmitters. Enhanced control panel lets the channels on the fly tochange the parameters of transceivers and see how it affects the system.
Allthis allows developers to rapidly build and debug the board. There was abetter means of rapid establishment of the project instead of QSys SOPSBuilder. Allows you to quickly connect QSyscompatible IPCores blocksinto a single system.
Additional improvements:
Improved Chip Planner (As for the settings of transceivers Stratix FPGA V);
adds support for 64bit Windows and Linux for the DSP Builder
added another IP Core Deinterlacer II IP core
improved support for Cyclone IV GX FPGAs and MAX V CPLDs (see final timing model can be generated and POF).
Finally Improved the problem with the Cyrillic alphabet in a text editor!))

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