Cadence SPB OrCAD 16.5.021 (Allegro SPB) Hotfix

Cadence SPB OrCAD 16.5.021 (Allegro SPB) Hotfix | 629MB

Cadence OrCAD PCB design suites combine industry-leading, production-proven, and highly scalable PCB design applications to deliver complete schematic entry, simulation, and place-and-route solutions. With these powerful, intuitive tools that integrate seamlessly across the entire PCB design flow, engineers can quickly move products from conception to final output.Cadence Allegro and OrCAD 16.5 provides customers with new capabilities for a shorter, predictable, and convergent path to product creation. The latest Allegro technology is now available through flexible on-demand product configurations that offer cost-efficiency and scalability. Allegro 16.5 spans silicon, SoC, and system-level development and offers PCB designers benefits such as:

- Higher functional density with a constraint-driven flow for embedded components
- Faster timing closure with new PCB interconnect design planning technology
- Fewer physical prototype iterations with concurrent team design authoring
- More efficient low-power design with integrated power delivery network analysis
- A compliant and faster implementation path with package/board-aware SoC IP
- Smoother collaboration among global teams with new SiP distributed co-design
- Flexibility through "base plus options" configurations

Fixed in Cadence SPB OrCAD 16.5.021
-- DATE: 05-5-2012 HOTFIX VERSION: 021

642550 ALLEGRO_EDITOR EDIT_ETCH Route connect of Diff Pairs is not honoring the correct gap when entering a region.
921837 CONCEPT_HDL CONSTRAINT_MGR DIFFERENTIAL_PAIR property in synonymed net is deleted automatically
926776 CONCEPT_HDL CORE Modify the newgenasym log file to convey the multi format vector information
969547 SCM CONSTRAINT_MGR Diff Pair, Net Class objects are being "corrupted" by making logic changes in ASA involving copy & paste of signals.
976566 PCB_LIBRARIAN VIEWERS SCM crashes when adding a part.
984538 PCB_LIBRARIAN CORE PDV and con2con crash on part having illegal data into symbol view
987120 CONCEPT_HDL ARCHIVER Customer would like to include signal models into archived project by Arciver.
988683 CONCEPT_HDL INFRA CMGR Net extraction via DEHDL writes topology file at the CPM project level
989116 CONCEPT_HDL CORE Warning 171: Port exist in symbol but not in schematic
990630 FSP TERMINATIONS Overlap of parts sig_name ctaps and refdes after schgen
992075 CONCEPT_HDL ARCHIVER Create Single File Archive and Delete Archived Directory doesnt work if spaces are found
993084 CONCEPT_HDL CONSTRAINT_MGR Problem with bus members
994466 SCM ECO SCM is going out of Memory in Import ECO Netlist which is used in the BRD2ASA flow
996609 APD EDIT_ETCH Error (SPMHAC-31): The element from which you are connecting is not on the subclass. Use "Add Via"
997076 CONSTRAINT_MGR OTHER Application not checking to class to class inherited spacing Cset
997655 CONSTRAINT_MGR CONCEPT_HDL Support Partical DCF import/Export in DEHDL
998176 SIG_INTEGRITY OTHER Allegro crashes when extracting net from CM
999044 ALLEGRO_EDITOR EDIT_ETCH Routing wires is confusing because of the way DRC engine resolves spacing rules.
999218 SIG_INTEGRITY OTHER concept2cm has encountered a problem
1001742 ALLEGRO_EDITOR SCHEM_FTB netrev detects an error for the part which has JEDEC_TYPE with null value.
1001897 SIG_INTEGRITY OTHER Packaging much longer in 16.5 s018 ISR
1001913 APD STREAM_IF Mirrored text is not mirrored in stream_out and stream_in
1001953 ALLEGRO_EDITOR OTHER Allegro 16.5 database crashes when trying to downrev to 16.3
1002895 SIG_INTEGRITY FIELD_SOLVERS Delay calculation is changed from ISR16 to ISR17 and above
1003097 APD WIREBOND How to change finger padstack that maintaining current finger angle
1003638 ALLEGRO_EDITOR UI_FORMS Ability to filter and sort in IDX Flow Manager Export/Import
1004196 ALLEGRO_EDITOR DRC_CONSTR Thermal ties creates shorts with Enable online DRC checked.
1004346 CONCEPT_HDL COMP_BROWSER The hyper-link under the DATASHEET column breaks after sorting
1004363 ALLEGRO_EDITOR PLACEMENT Place manual is inaccurate at pick up
1005265 CONCEPT_HDL INFRA Uprev from 163 to 165 does not complete
1005398 SCM SCHGEN Crash when generating schematics when vectored pins tied to non vector signal
1005584 ALLEGRO_EDITOR MANUFACT Variant Assembly Drawing with locked symbols creates incorrect view
1006266 ALLEGRO_EDITOR GRAPHICS 3D Viewer Crashes Allegro
1007420 ALLEGRO_EDITOR OTHER Allegro PCB Editor crashes while doing a File > Change Editor

Company Profile

To keep pace with market demand for more performance and functionality in today's mobile phones, digital cameras, computers, automotive systems and other electronics products, manufacturers pack billions of transistors onto a single chip. This massive integration parallels the shift to ever-smaller process geometries, where the chip's transistors and other physical features can be smaller than the wavelength of light used to print them.

Designing and manufacturing semiconductor devices with such phenomenal scale, complexity and technological challenges would not be possible without electronic design automation (EDA). It is essential for everything from verifying that the myriad transistors do what the designer intended to dealing with physical effects on electrons traveling miles of wires with widths sometimes measuring less than 100 nanometers.

Cadence Design Systems is the world's leading EDA company. Cadence customers use our software, hardware, and services to overcome a range of technical and economic hurdles.

Name: Cadence SPB OrCAD
Version: 16.5.021 (Allegro SPB) 32bit Hotfix
Interface: english
OS: Windows XP / Vista / Seven
System Requirements: Cadence SPB/OrCAD 16.50.000 - 16.50.020
OS: Windows XP / Vista / Seven

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